US 12,002,727 B2
Barrier structures for underfill containment
Ziyin Lin, Chandler, AZ (US); Vipul Mehta, Chandler, AZ (US); Wei Li, Chandler, AZ (US); Edvin Cetegen, Chandler, AZ (US); Xavier Brun, Hillsboro, OR (US); Yang Guo, Chandler, AZ (US); Soud Choudhury, Chandler, AZ (US); Shan Zhong, Chandler, AZ (US); Christopher Rumer, Chander, AZ (US); Nai-Yuan Liu, Chandler, AZ (US); Ifeanyi Okafor, Chandler, AZ (US); and Hsin-Wei Wang, Chandler, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by INTEL CORPORATION, Santa Clara, CA (US)
Filed on Feb. 11, 2020, as Appl. No. 16/788,186.
Prior Publication US 2021/0249322 A1, Aug. 12, 2021
Int. Cl. H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 23/367 (2006.01)
CPC H01L 23/3185 (2013.01) [H01L 23/3675 (2013.01); H01L 23/562 (2013.01); H01L 24/16 (2013.01); H01L 2224/16227 (2013.01); H01L 2924/18161 (2013.01); H01L 2924/35121 (2013.01)] 13 Claims
OG exemplary drawing
 
1. An integrated circuit assembly, comprising:
an electronic substrate;
a first integrated circuit device having a first surface, an opposing second surface, a first side extending between the first surface and the second surface, and a first edge defined at an intersection of the second surface and the first side of the first integrated circuit device, wherein the first surface of the first integrated circuit device is electrically attached to the electronic substrate;
a second integrated circuit device having a first surface, an opposing second surface, and a second side extending between the first surface and the second surface, and a second edge defined at an intersection of the second surface and the second side of the second integrated circuit device, wherein the first surface of the second integrated circuit device is electrically attached to the electronic substrate;
an underfill material between the first side of the first integrated circuit device and the second side of the second integrated circuit device; and
a trench within at least one of the first side of the first integrated circuit device or the second surface of the second integrated circuit device, the trench adjacent to, but laterally spaced a first distance apart from, the first edge or second edge, wherein the underfill material does not fill the trench.