US 12,002,716 B2
Method of manufacturing a semiconductor device and a semiconductor device
Shu-Wen Shen, Hsinchu (TW); and Chen-Ping Chen, Toucheng Township (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Mar. 13, 2023, as Appl. No. 18/120,902.
Application 18/120,902 is a continuation of application No. 17/368,496, filed on Jul. 6, 2021, granted, now 11,605,727, issued on Mar. 14, 2023.
Claims priority of provisional application 63/168,795, filed on Mar. 31, 2021.
Prior Publication US 2023/0215933 A1, Jul. 6, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/8234 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/775 (2006.01); H01L 29/786 (2006.01)
CPC H01L 21/823481 (2013.01) [H01L 21/823412 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 29/0665 (2013.01); H01L 29/42392 (2013.01); H01L 29/66439 (2013.01); H01L 29/6653 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/6656 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01); H01L 29/0673 (2013.01); H01L 29/775 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
9. A method of manufacturing a semiconductor device, comprising:
forming fin structures each including a stacked layer of first semiconductor layers and second semiconductor layers disposed over a bottom fin structure and a hard mask layer over the stacked layer;
forming an isolation insulating layer so that the hard mask layer and the stacked layer are exposed from the isolation insulating layer;
forming a sacrificial cladding layer over the exposed hard mask layer and stacked layer;
performing an etching operation to remove lateral portions of the sacrificial cladding layer, thereby leaving the sacrificial cladding layer on sidewalls of the exposed hard mask layer and stacked layer, wherein during the etching operation, a protection layer is formed over the sacrificial cladding layer;
forming a wall fin structure between the fin structures;
removing the hard mask layer;
forming a sacrificial gate structure over the fin structures;
forming sidewall spacers on sidewalls of the sacrificial gate structure and sidewalls of a part of the wall fin structure;
forming a source/drain structure over the fin structures adjacent the sidewall spacers;
forming a dielectric layer over the source/drain structure;
removing the sacrificial gate structure;
removing the sacrificial cladding layer;
removing the first semiconductor layers; and
forming a metal gate structure around the second semiconductor layers.