US 12,002,689 B2
Semiconductor equipment regulation method and semiconductor device fabrication method
Xifei Bao, Hefei (CN); and Runsheng Shen, Hefei (CN)
Assigned to Changxin Memory Technologies, Inc., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Nov. 18, 2021, as Appl. No. 17/455,515.
Application 17/455,515 is a continuation of application No. PCT/CN2021/097613, filed on Jun. 1, 2021.
Claims priority of application No. 202010547902.2 (CN), filed on Jun. 16, 2020.
Prior Publication US 2022/0076969 A1, Mar. 10, 2022
Int. Cl. H01L 21/00 (2006.01); H01L 21/67 (2006.01); H10B 12/00 (2023.01)
CPC H01L 21/67069 (2013.01) [H01L 21/67253 (2013.01); H10B 12/03 (2023.02)] 16 Claims
OG exemplary drawing
 
1. A semiconductor equipment regulation method, comprising:
providing a simulated wafer;
placing the simulated wafer in an etching chamber, and conditioning a temperature in the etching chamber by using a temperature control device while performing an etching process on the simulated wafer by using an etching gas; during the etching process, a polymer layer is formed on a surface of the simulated wafer;
measuring a thickness of the polymer layer and acquiring a thickness distribution map;
comparing the acquired thickness distribution map with a target thickness distribution map; and
adjusting a temperature control effect through using the temperature control device on each region of the simulated wafer according to a result of the comparison, so as to adjust a thickness of the polymer layer formed during a next etching process.