US 12,002,678 B2
Gate spacing in integrated circuit structures
Charles Henry Wallace, Portland, OR (US); Mohit K. Haran, Hillsboro, OR (US); Paul A. Nyhus, Portland, OR (US); Gurpreet Singh, Portland, OR (US); Eungnak Han, Portland, OR (US); David Nathan Shykind, Buxton, OR (US); and Sean Michael Pursel, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 25, 2020, as Appl. No. 17/033,228.
Prior Publication US 2022/0102148 A1, Mar. 31, 2022
Int. Cl. H01L 21/28 (2006.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 21/308 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01)
CPC H01L 21/28123 (2013.01) [H01L 21/02603 (2013.01); H01L 21/30604 (2013.01); H01L 21/308 (2013.01); H01L 21/823412 (2013.01); H01L 21/823418 (2013.01); H01L 21/823437 (2013.01); H01L 27/088 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/66636 (2013.01); H01L 29/66742 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) structure, comprising:
a first gate metal having a longitudinal axis;
a second gate metal, wherein the longitudinal axis of the first gate metal is aligned with a longitudinal axis of the second gate metal;
a first gate contact above the first gate metal;
a second gate contact above the second gate metal; and
an unordered region having an unordered lamellar pattern, wherein the unordered region is coplanar with the first gate contact and the second gate contact.