US 12,002,627 B2
Multilayer electronic component and method of manufacturing the same
Tae Gyeom Lee, Suwon-si (KR); Gi Long Kim, Suwon-si (KR); Seon Jae Mun, Suwon-si (KR); Byung Rok Ahn, Suwon-si (KR); and Kyoung Jin Cha, Suwon-si (KR)
Assigned to SAMSUNG ELECTRO-MECHANICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRO-MECHANICS CO., LTD., Suwon-si (KR)
Filed on May 20, 2022, as Appl. No. 17/749,709.
Claims priority of application No. 10-2021-0190625 (KR), filed on Dec. 29, 2021.
Prior Publication US 2023/0207209 A1, Jun. 29, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01G 4/30 (2006.01); H01G 4/008 (2006.01); H01G 4/012 (2006.01); H01G 4/12 (2006.01); H01G 4/224 (2006.01)
CPC H01G 4/30 (2013.01) [H01G 4/008 (2013.01); H01G 4/012 (2013.01); H01G 4/1218 (2013.01); H01G 4/224 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A multilayer electronic component comprising:
a body including a plurality of dielectric layers and a plurality of internal electrodes alternately disposed with the dielectric layers in a first direction, and having first and second surfaces facing each other in the first direction, third and fourth surfaces connected to the first and second surfaces and facing each other in a second direction, and fifth and sixth surfaces connected to the first to fourth surfaces and facing each other in a third direction; and
external electrodes disposed on the body,
wherein when a space where the plurality of internal electrodes overlap each other in the first direction is defined as a capacitance forming portion, the plurality of internal electrodes include internal electrodes that are curved at end portions thereof in the capacitance forming portion and internal electrodes that are flat in the capacitance forming portion, and
in a cross section of the body in the first and second directions, (F1+F2)/D1×100 is 20 or less, where F1 is a maximum distance from an uppermost internal electrode to an uppermost flat internal electrode in the first direction, F2 is a maximum distance from a lowermost internal electrode to a lowermost flat internal electrode in the first direction, and D1 is a thickness of the capacitance forming portion in the first direction at the center thereof in the second direction, and
the external electrodes include first and second external electrodes disposed on the third and fourth surfaces, respectively, and the plurality of internal electrodes includes the first internal electrodes connected to the first external electrode at the third surface, and second internal electrodes connected to the second external electrode at the fourth surface.