US 12,002,543 B2
Memory device for supporting new command input scheme and method of operating the same
Youngcheon Kwon, Hwaseong-si (KR); Jemin Ryu, Seoul (KR); Jaeyoun Youn, Seoul (KR); Haesuk Lee, Seongnam-si (KR); and Jihyun Choi, Daegu (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Apr. 12, 2023, as Appl. No. 18/299,440.
Application 18/299,440 is a continuation of application No. 17/574,174, filed on Jan. 12, 2022, granted, now 11,636,885.
Application 17/574,174 is a continuation of application No. 17/145,941, filed on Jan. 11, 2021, granted, now 11,250,894, issued on Feb. 15, 2022.
Claims priority of application No. 10-2020-0008110 (KR), filed on Jan. 21, 2020; and application No. 10-2020-0103438 (KR), filed on Aug. 18, 2020.
Prior Publication US 2023/0245690 A1, Aug. 3, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 7/22 (2006.01); G11C 7/10 (2006.01)
CPC G11C 7/222 (2013.01) [G11C 7/1048 (2013.01); G11C 7/1057 (2013.01); G11C 7/1084 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a clock pin configured to receive a clock signal;
row pins configured to receive a first active command and a first precharge command during a first time period, and receive a second active command and a second precharge command during a second time period; and
column pins configured to receive a first read command or a first write command during the first time period, and receive a second read command or a second write command during the second time period,
wherein during the first time period, the row pins are configured to receive the first active command during a first sub-period and receive the first precharge command during a second sub-period corresponding to a rising edge of the clock signal after receiving the first active command, and the column pins are configured to receive the first read command or the first write command during a third sub-period,
wherein during the second time period, the row pins are configured to receive the second active command during a fourth sub-period and receive the second precharge command during a fifth sub-period corresponding to a falling edge of the clock signal after receiving the second active command, and the column pins are configured to receive the second read command or the second write command during a sixth sub-period,
wherein a length of each of the first sub-period and the fourth sub-period is one and a half (1.5) cycles of the clock signal, a length of each of the second sub-period and the fifth sub-period is a half (0.5) cycle of the clock signal, and a length each of the third sub-period and the sixth sub-period is one (1) cycle of the clock signal.