US 12,002,540 B2
On-die termination of address and command signals
Ian Shaeffer, Los Gatos, CA (US); and Kyung Suk Oh, Cupertino, CA (US)
Assigned to RAMBUS INC., San Jose, CA (US)
Filed by Rambus Inc., San Jose, CA (US)
Filed on Jun. 26, 2023, as Appl. No. 18/214,466.
Application 18/214,466 is a continuation of application No. 17/954,223, filed on Sep. 27, 2022, granted, now 11,688,441.
Application 17/954,223 is a continuation of application No. 17/222,388, filed on Apr. 5, 2021, granted, now 11,468,928, issued on Oct. 11, 2022.
Application 17/222,388 is a continuation of application No. 16/933,891, filed on Jul. 20, 2020, granted, now 10,971,201, issued on Apr. 6, 2021.
Application 16/933,891 is a continuation of application No. 16/716,385, filed on Dec. 16, 2019, granted, now 10,720,196, issued on Jul. 21, 2020.
Application 16/716,385 is a continuation of application No. 16/174,180, filed on Oct. 29, 2018, granted, now 10,510,388, issued on Dec. 17, 2019.
Application 16/174,180 is a continuation of application No. 15/665,304, filed on Jul. 31, 2017, granted, now 10,115,439, issued on Oct. 30, 2018.
Application 15/665,304 is a continuation of application No. 15/394,009, filed on Dec. 29, 2016, granted, now 9,721,629, issued on Aug. 1, 2017.
Application 15/394,009 is a continuation of application No. 15/081,745, filed on Mar. 25, 2016, granted, now 9,570,129, issued on Feb. 14, 2017.
Application 15/081,745 is a continuation of application No. 14/613,270, filed on Feb. 3, 2015, granted, now 9,299,407, issued on Mar. 26, 2016.
Application 14/613,270 is a continuation of application No. 14/088,277, filed on Nov. 22, 2013, granted, now 8,947,962, issued on Feb. 3, 2015.
Application 14/088,277 is a continuation of application No. 12/519,908, granted, now 8,599,631, issued on Dec. 3, 2013, previously published as PCT/US2007/088245, filed on Dec. 19, 2007.
Claims priority of provisional application 60/876,672, filed on Dec. 21, 2006.
Prior Publication US 2024/0105242 A1, Mar. 28, 2024
Int. Cl. G11C 5/06 (2006.01); G11C 7/22 (2006.01); G11C 11/4063 (2006.01); G11C 29/02 (2006.01); G11C 5/02 (2006.01); G11C 5/04 (2006.01); G11C 7/18 (2006.01); G11C 11/4097 (2006.01)
CPC G11C 7/22 (2013.01) [G11C 5/063 (2013.01); G11C 11/4063 (2013.01); G11C 29/02 (2013.01); G11C 29/022 (2013.01); G11C 29/025 (2013.01); G11C 29/028 (2013.01); G11C 5/025 (2013.01); G11C 5/04 (2013.01); G11C 5/06 (2013.01); G11C 7/18 (2013.01); G11C 11/4097 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory controller to control the operation of a memory device, the memory controller comprising:
a command/address (CA) transmission circuit;
the memory controller to:
send, using the CA transmission circuit, command/address (CA) signals via a CA bus to respective inputs of the memory device and a chip select signal to a chip select input of the memory device; and
send to the memory device:
register values, for storage in a plurality of registers of the memory device, including a register value that selects from two or more impedance values of on-die termination (ODT) impedances to apply to each of the respective inputs of the memory device that receive the CA signals;
wherein the register values include one or more register values to selectively enable application of the ODT impedances to the respective inputs that receive the CA signals, and a register value that selectively enables application of a CS ODT impedance to the chip select input.