US 12,002,539 B2
Memory device and memory array structure using charge sharing for multi-bit convolutional neural network based computing-in-memory applications, and computing method thereof
Meng-Fan Chang, Hsinchu (TW); Yen-Chi Chou, Hsinchu (TW); and Jian-Wei Su, Hsinchu (TW)
Assigned to NATIONAL TSING HUA UNIVERSITY, Hsinchu (TW)
Filed by NATIONAL TSING HUA UNIVERSITY, Hsinchu (TW)
Filed on Aug. 4, 2020, as Appl. No. 16/985,205.
Prior Publication US 2022/0044714 A1, Feb. 10, 2022
Int. Cl. G11C 11/54 (2006.01); G11C 5/06 (2006.01); G11C 7/10 (2006.01); G11C 7/12 (2006.01); G11C 8/08 (2006.01); G11C 8/16 (2006.01); G11C 11/419 (2006.01)
CPC G11C 7/12 (2013.01) [G11C 5/06 (2013.01); G11C 7/1006 (2013.01); G11C 8/08 (2013.01); G11C 8/16 (2013.01); G11C 11/419 (2013.01); G11C 11/54 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, wherein the memory device uses charge sharing for multi-bit convolutional neural network based computing-in-memory applications, and the memory device is controlled by a first word line, a second word line, an enable signal, a first switching signal, and a second switching signal, the memory device comprising:
at least one memory cell storing a weight, wherein the at least one memory cell is controlled by the first word line and comprises a local bit line transmitting the weight; and
a computational cell connected to the at least one memory cell and receiving the weight via the local bit line, wherein the computational cell comprises an input bit line, an input bit line bar, an output bit line and an output bit line bar, each of the input bit line and the input bit line bar transmits a multi-bit input value, the computational cell is controlled by the second wordline and the enable signal to generate a multi-bit output value on each of the output bit line and the output bit line bar according to the multi-bit input value multiplied by the weight, and the computational cell is controlled by the first switching signal and the second switching signal for charge sharing.