	US 12,002,535 B2
	Semiconductor device comprising memory cell array and arithmetic circuit
Takeshi Aoki, Kanagawa (JP); Munehiro Kozuma, Kanagawa (JP); Masashi Fujita, Tokyo (JP); and Takahiko Ishizu, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Appl. No. 17/640,452
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
PCT Filed Sep. 8, 2020, PCT No. PCT/IB2020/058318 § 371(c)(1), (2) Date Mar. 4, 2022, PCT Pub. No. WO2021/053453, PCT Pub. Date Mar. 25, 2021.
Claims priority of application No. 2019-172147 (JP), filed on Sep. 20, 2019.
Prior Publication US 2022/0343954 A1, Oct. 27, 2022
Int. Cl. G11C 11/24 (2006.01); G11C 7/06 (2006.01); G11C 7/08 (2006.01); G11C 11/4091 (2006.01); G11C 11/54 (2006.01)

CPC G11C 7/065 (2013.01) [G11C 7/08 (2013.01); G11C 11/4091 (2013.01); G11C 11/54 (2013.01)]

15 Claims

1. A semiconductor device comprising:

a memory cell array;

a sense amplifier circuit; and

an arithmetic circuit,

wherein the memory cell array comprises m×n memory cells and at least n wirings,

wherein m and n are each an integer of 2 or more,

wherein the m×n memory cells are arranged in a matrix,

wherein the sense amplifier circuit comprises at least n first circuits,

wherein each of the n wirings is electrically connected to m of the memory cells,

wherein the n wirings are electrically connected to the n first circuits,

wherein the arithmetic circuit comprises s second circuits,

wherein s is an integer of 1 or more and n or less,

wherein the second circuit is electrically connected to t of the first circuits,

wherein t is an integer of 1 or more and s×t is an integer of n or less,

wherein the second circuit performs an arithmetic operation using a signal of a weight coefficient output from the first circuit, and

wherein the s second circuits perform parallel arithmetic operations.