US 12,002,531 B2
Techniques for retiring blocks of a memory system
Deping He, Boise, ID (US); Jonathan S. Parry, Boise, ID (US); and Chun Sum Yeung, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jan. 19, 2022, as Appl. No. 17/648,396.
Claims priority of provisional application 63/233,065, filed on Aug. 13, 2021.
Prior Publication US 2023/0049201 A1, Feb. 16, 2023
Int. Cl. G11C 29/42 (2006.01); G06F 11/07 (2006.01); G11C 29/12 (2006.01); G11C 29/20 (2006.01); G11C 29/44 (2006.01)
CPC G11C 29/42 (2013.01) [G06F 11/076 (2013.01); G11C 29/1201 (2013.01); G11C 29/20 (2013.01); G11C 29/4401 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A memory system, comprising:
one or more memory devices comprising a block of memory cells; and
processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:
determine an occurrence of at least one error for the block of memory cells;
select one or more operating conditions of a plurality of operating conditions associated with the block of memory cells based at least in part on determining the occurrence of the at least one error;
determine whether to retire the block of memory cells based at least in part on determining the occurrence of the at least one error and selecting the one or more operating conditions associated with the block of memory cells; and
retire the block of memory cells based at least in part on the block of memory cells including the at least one error and the one or more operating conditions satisfying a respective criteria.