US 12,002,530 B2
Embedded memory transparent in-system built-in self-test
Grigor Tshagharyan, Yerevan (AM); Gurgen Harutyunyan, Yerevan (AM); Samvel Shoukourian, Yerevan (AM); and Yervant Zorian, Santa Clara, CA (US)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Oct. 31, 2022, as Appl. No. 17/977,599.
Claims priority of provisional application 63/274,127, filed on Nov. 1, 2021.
Prior Publication US 2023/0140090 A1, May 4, 2023
Int. Cl. G11C 29/12 (2006.01)
CPC G11C 29/12 (2013.01) 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) device, comprising:
a memory system comprising multiple memory cells;
control circuitry configured to preclude functional circuitry from accessing the memory cells during test sessions;
one or more registers; and
memory built-in self-test (MBIST) circuitry configured to test subsets of the memory cells during the test sessions, including to store contents of the subsets of the memory cells in the one or more registers prior to testing the respective subsets of the memory cells, and restore the contents of the subsets of the memory cells from the one or more registers subsequent to testing the respective subsets of the memory cells.