CPC G11C 29/12 (2013.01) | 20 Claims |
1. An integrated circuit (IC) device, comprising:
a memory system comprising multiple memory cells;
control circuitry configured to preclude functional circuitry from accessing the memory cells during test sessions;
one or more registers; and
memory built-in self-test (MBIST) circuitry configured to test subsets of the memory cells during the test sessions, including to store contents of the subsets of the memory cells in the one or more registers prior to testing the respective subsets of the memory cells, and restore the contents of the subsets of the memory cells from the one or more registers subsequent to testing the respective subsets of the memory cells.
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