US 12,002,529 B2
Shift register, semiconductor device, display device, and electronic device
Atsushi Umezaki, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
Filed on Jun. 2, 2023, as Appl. No. 18/205,000.
Application 18/205,000 is a continuation of application No. 17/246,842, filed on May 3, 2021, granted, now 11,699,497.
Application 17/246,842 is a continuation of application No. 16/424,813, filed on May 29, 2019, granted, now 11,011,244, issued on May 18, 2021.
Application 16/424,813 is a continuation of application No. 15/584,117, filed on May 2, 2017, granted, now 10,311,960, issued on Jun. 4, 2019.
Application 15/584,117 is a continuation of application No. 14/800,765, filed on Jul. 16, 2015, granted, now 9,646,714, issued on May 9, 2017.
Application 14/800,765 is a continuation of application No. 11/539,429, filed on Oct. 6, 2006, granted, now 9,153,341, issued on Oct. 6, 2015.
Claims priority of application No. 2005-303771 (JP), filed on Oct. 18, 2005.
Prior Publication US 2023/0317190 A1, Oct. 5, 2023
Int. Cl. G11C 19/18 (2006.01); G09G 3/36 (2006.01); G09G 3/3266 (2016.01)
CPC G11C 19/184 (2013.01) [G09G 3/3648 (2013.01); G09G 3/3677 (2013.01); G09G 3/3266 (2013.01); G09G 2300/0426 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0275 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/0289 (2013.01); G09G 2320/02 (2013.01); G09G 2320/043 (2013.01); G09G 2330/021 (2013.01); G09G 2330/023 (2013.01)] 4 Claims
OG exemplary drawing
 
1. A display device comprising:
a gate driver comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; and
a pixel comprising an eighth transistor,
wherein one of a source and a drain of the first transistor is electrically connected to a gate signal line,
wherein the other of the source and the drain of the first transistor is electrically connected to a clock signal line,
wherein a gate of the first transistor is electrically connected to one of a source and a drain of the third transistor,
wherein one of a source and a drain of the second transistor is electrically connected to the gate signal line,
wherein the other of the source and the drain of the second transistor is electrically connected to a first power source line,
wherein a gate of the second transistor is electrically connected to a gate of the fourth transistor,
wherein the other of the source and the drain of the third transistor is electrically connected to a second power source line,
wherein a gate of the third transistor is electrically connected to a first wiring to which a start pulse is input,
wherein one of a source and a drain of the fourth transistor is electrically connected to the gate of the first transistor,
wherein the other of the source and the drain of the fourth transistor is electrically connected to a third power source line,
wherein one of a source and a drain of the fifth transistor is electrically connected to the gate of the first transistor,
wherein the other of the source and the drain of the fifth transistor is electrically connected to the third power source line,
wherein a gate of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor,
wherein the other of the source and the drain of the sixth transistor is electrically connected to a second wiring,
wherein a gate of the sixth transistor is electrically connected to one of a source and a drain of the seventh transistor,
wherein the other of the source and the drain of the seventh transistor is electrically connected to the third power source line,
wherein a gate of the seventh transistor is electrically connected to the gate of the first transistor, and
wherein a gate of the eighth transistor is electrically connected to the gate signal line.