US 12,002,526 B2
Defect detection during program verify in a memory sub-system
Pinchou Chiang, San Jose, CA (US); Arvind Muralidharan, Folsom, CA (US); James I. Esteves, El Dorado Hills, CA (US); Michele Piccardi, Cupertino, CA (US); and Theodore T. Pekny, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 29, 2022, as Appl. No. 17/707,766.
Application 17/707,766 is a continuation of application No. 15/929,439, filed on May 1, 2020, granted, now 11,315,647.
Prior Publication US 2022/0223215 A1, Jul. 14, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/3459 (2013.01) [G11C 16/0483 (2013.01); G11C 16/10 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory array comprising a plurality of wordlines;
a defect detector circuit coupled to the memory array, wherein the defect detector circuit is configured to sample a load current from a selected wordline of the plurality of wordlines during a program verify phase of a program operation associated with the selected wordline, generate a measured output voltage that modulates with respect to the load current, and perform a comparison of the measured output voltage to a reference voltage; and
control logic coupled to the defect detector circuit, wherein the control logic is configured to identify a presence of a defect on the selected wordline in view of the comparison of the measured output voltage to the reference voltage.