US 12,002,524 B2
Sequential wordline erase verify schemes
Ronit Roneel Prakash, Hiratsuka (JP); Jiun-Horng Lai, Kamakura (JP); Chengkuan Yin, Tokyo (JP); and Shinji Sato, Sagamihara (JP)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 21, 2022, as Appl. No. 18/085,783.
Application 18/085,783 is a continuation of application No. 17/335,132, filed on Jun. 1, 2021, granted, now 11,574,690.
Prior Publication US 2023/0117364 A1, Apr. 20, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/34 (2006.01); G11C 16/04 (2006.01)
CPC G11C 16/3445 (2013.01) [G11C 16/0483 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory array comprising a plurality of wordline groups, wherein each wordline group of the plurality of wordline groups comprises a set of even wordlines and a set of odd wordlines; and
control logic, operatively coupled with the memory array, to perform operations comprising:
identifying, from the plurality of wordline groups, a set of passing wordline groups and a set of failing wordline groups, wherein the set of passing wordline groups comprises at least one passing wordline group determined to have passed a first erase verify of an erase verify process, and wherein the set of failing wordline groups comprises at least one failing wordline group determined to have failed the first erase verify;
causing an inhibiting bias voltage to be applied with respect to each passing wordline group of the set of passing wordline groups; and
causing a second erase verify of the erase verify process to be performed sequentially with respect to each failing wordline group of the set of failing wordline groups.