US 12,002,518 B2
Memory device performing temperature compensation and operating method thereof
Yongsung Cho, Hwaseong-si (KR); Kyoman Kang, Gunpo-si (KR); Minhwi Kim, Hwaseong-si (KR); Ilhan Park, Suwon-si (KR); and Jinyoung Chun, Seoul (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Mar. 31, 2022, as Appl. No. 17/710,283.
Claims priority of application No. 10-2021-0108964 (KR), filed on Aug. 18, 2021.
Prior Publication US 2023/0055963 A1, Feb. 23, 2023
Int. Cl. G11C 16/00 (2006.01); G11C 16/04 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01)
CPC G11C 16/24 (2013.01) [G11C 16/0483 (2013.01); G11C 16/26 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory cell array including a plurality of memory cells;
a page buffer circuit connected to the memory cell array through a plurality of bit lines and comprising a page buffer connected to each of the plurality of bit lines, the page buffer comprising at least one first latch for storing data based on a voltage level of a first sensing node; and
a control circuit configured to adjust a level of a voltage signal provided to the page buffer circuit,
wherein the page buffer further comprises a trip control transistor arranged between the at least one first latch and the first sensing node, and
wherein the control circuit is further configured to, based on a read operation being performed on the memory cell array, control a trip control voltage to be provided to a gate of the trip control transistor, and control a level of the trip control voltage to vary according to a temperature of the memory device.