CPC G11C 16/10 (2013.01) [G11C 16/0483 (2013.01); G11C 16/3459 (2013.01); G11C 8/12 (2013.01)] | 20 Claims |
1. A nonvolatile memory comprising:
a first memory cell array including a first selection transistor connected to a first string selection line;
a second memory cell array including a second selection transistor connected to a second string selection line and spaced apart from the first string selection line by a first cutting line; and
a peripheral circuit configured to;
provide a first program voltage to the first selection transistor,
provide a second program voltage to the second selection transistor different from the first program voltage,
program the first selection transistor with a first threshold voltage in response to the first program voltage, and
program the second selection transistor with a second threshold voltage level greater than the first threshold voltage in response to the second program voltage.
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