CPC G11C 11/4096 (2013.01) [G11C 11/4076 (2013.01); G11C 11/4087 (2013.01); G11C 11/4093 (2013.01)] | 25 Claims |
1. An apparatus, comprising:
a memory device comprising a first set of memory cells and a second set of memory cells, a resiliency of the first set of memory cells against being repeatedly opened for a threshold duration or longer being greater than a resiliency of the second set of memory cells against being repeatedly opened for the threshold duration or longer; and
a controller coupled with the memory device and configured to cause the apparatus to:
receive a command associated with an access duration;
determine whether to access, as part of executing the command, the first set of memory cells or the second set of memory cells based at least in part on the access duration; and
access, for the access duration as part of executing the command, the first set of memory cells based at least in part on the access duration being greater than the threshold duration or the second set of memory cells based at least in part on the access duration being less than or equal to the threshold duration.
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