US 12,002,502 B2
Memory device and refresh method thereof
Seungki Hong, Incheon (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Aug. 5, 2022, as Appl. No. 17/882,242.
Claims priority of application No. 10-2022-0032886 (KR), filed on Mar. 16, 2022.
Prior Publication US 2023/0298655 A1, Sep. 21, 2023
Int. Cl. G11C 11/406 (2006.01); G11C 29/00 (2006.01)
CPC G11C 11/40622 (2013.01) [G11C 11/40615 (2013.01); G11C 29/783 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory cell array comprising a plurality of rows; and
a refresh control circuit comprising a plurality of registers each configured to store a row address,
wherein the refresh control circuit is configured to:
determine, based on an incoming row address satisfying a replacement condition, in a first determination, whether to replace a first row address stored in a first register among the plurality of registers with the incoming row address based on a replacement probability;
maintain the first row address stored in the first register or replace the first row address stored in the first register with the incoming row address based on a first result of the first determination; and
determine, in a second determination, a victim row address to be refreshed based on a second row address stored in a second register among the plurality of registers.