CPC G11C 11/40622 (2013.01) [G11C 11/40615 (2013.01); G11C 29/783 (2013.01)] | 20 Claims |
1. A memory device comprising:
a memory cell array comprising a plurality of rows; and
a refresh control circuit comprising a plurality of registers each configured to store a row address,
wherein the refresh control circuit is configured to:
determine, based on an incoming row address satisfying a replacement condition, in a first determination, whether to replace a first row address stored in a first register among the plurality of registers with the incoming row address based on a replacement probability;
maintain the first row address stored in the first register or replace the first row address stored in the first register with the incoming row address based on a first result of the first determination; and
determine, in a second determination, a victim row address to be refreshed based on a second row address stored in a second register among the plurality of registers.
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