US 12,002,498 B2
Coaxial top MRAM electrode
Oscar van der Straten, Guilderland Center, NY (US); Koichi Motoyama, Clifton Park, NY (US); and Chih-Chao Yang, Glenmont, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Jun. 14, 2022, as Appl. No. 17/806,790.
Prior Publication US 2023/0402079 A1, Dec. 14, 2023
Int. Cl. G11C 11/15 (2006.01); G11C 11/16 (2006.01); H10B 61/00 (2023.01); H10N 50/01 (2023.01); H10N 50/10 (2023.01); H10N 50/80 (2023.01)
CPC G11C 11/161 (2013.01) [H10B 61/00 (2023.02); H10N 50/01 (2023.02); H10N 50/10 (2023.02); H10N 50/80 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a first magneto-resistive random access memory (MRAM) pillar, comprising:
a bottom electrode layer;
a reference layer connected above the bottom electrode layer;
a free layer; and
a tunnel barrier between the reference layer and the free layer, wherein the MRAM pillar comprises a pillar diameter; and
a coaxial top electrode comprising a top diameter that is less than the pillar diameter wherein the coaxial top electrode comprises an inner conductor core and an outer metal barrier shell.