| CPC G06F 9/4881 (2013.01) [G06F 9/30083 (2013.01); G06F 9/4837 (2013.01); G06F 9/485 (2013.01); G06F 9/4893 (2013.01); G06F 9/5027 (2013.01); G06F 9/5038 (2013.01); G06F 9/505 (2013.01); G06F 9/542 (2013.01); G06F 9/546 (2013.01); G06F 11/3024 (2013.01); G06F 11/3419 (2013.01); G06F 11/3433 (2013.01)] | 16 Claims |
|
1. A method of controlling an operation of a system on chip (SoC) including a processor comprising a plurality of processor cores, the method comprising:
the processor executing a kernel of an operating system to monitor a task queue of each of the processor cores for determining a task execution delay time for each task among a plurality of tasks respectively assigned to the plurality of processor cores, to generate a plurality of task execution delay times;
determining, by the kernel, a core execution delay time for each core among the plurality of processor cores from a single time among the task execution delay times associated with the tasks assigned to the corresponding core, to generate a plurality of core execution delay times, wherein the single time is a largest time among the task execution delay times associated with the tasks assigned to the corresponding core;
determining, by the kernel, whether a delay has occurred in a first processor core among the processor cores based on the core execution delay time of the first processor core;
outputting, by the kernel, a control request to a performance controller of the SoC when the kernel determines the delay has occurred; and
increasing, by the performance controller, a power level of the first processor core in response to receipt of the control request.
|