US 12,001,844 B2
Performance scaling for binary translation
Hee Jun Park, Redmond, WA (US); and Mehmet Iyigun, Redmond, WA (US)
Assigned to Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed by Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed on Mar. 16, 2023, as Appl. No. 18/185,122.
Application 18/185,122 is a continuation of application No. 17/510,167, filed on Oct. 25, 2021, granted, now 11,609,763.
Application 17/510,167 is a continuation of application No. 16/714,626, filed on Dec. 13, 2019, granted, now 11,157,279, issued on Oct. 26, 2021.
Application 16/714,626 is a continuation of application No. 16/273,080, filed on Feb. 11, 2019, granted, now 10,732,975, issued on Aug. 4, 2020.
Application 16/273,080 is a continuation of application No. 15/613,110, filed on Jun. 2, 2017, granted, now 10,235,178, issued on Mar. 19, 2019.
Prior Publication US 2023/0333854 A1, Oct. 19, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/30 (2018.01); G06F 8/52 (2018.01); G06F 9/38 (2018.01); G06F 9/48 (2006.01); G06F 9/50 (2006.01)
CPC G06F 9/30174 (2013.01) [G06F 8/52 (2013.01); G06F 9/30043 (2013.01); G06F 9/30083 (2013.01); G06F 9/3009 (2013.01); G06F 9/3836 (2013.01); G06F 9/4893 (2013.01); G06F 9/5094 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a processor configured to execute instructions according to a first instruction set architecture (ISA); and
memory coupled to the processor, the memory comprising computer executable instructions that, when executed by the processor, perform operations comprising:
varying an execution speed of an execution unit provided to the processor, based on a determination that the execution unit comprises a translated instruction or a native instruction, the varying the execution speed comprises:
based on the determination that the execution unit comprises a translated instruction, the translated instruction is executed using a high power-performance level that increases a default execution speed for the translated instruction, the translated instruction being an instruction translated from a second ISA to the first ISA; and
based on the determination that the execution unit comprises a native instruction, the native instruction is executed using a low power-performance level that decreases a default execution speed for the native instruction, the native instruction being an instruction in the first ISA.