CPC G06F 9/3004 (2013.01) [G06F 9/30134 (2013.01); G06F 9/461 (2013.01); G06F 21/52 (2013.01)] | 33 Claims |
1. A processor comprising:
a shadow stack pointer (SSP) register to store a current SSP for a current shadow stack;
a decode unit to decode an instruction to switch from the current shadow stack to a new shadow stack, the instruction having a memory operand to provide a memory address of a token stored on the new shadow stack; and
an execution unit coupled with the decode unit, the execution unit to perform operations corresponding to the instruction, including to:
load the token from the new shadow stack;
check that a portion of the token matches a portion of the memory address and that a least significant bit of the token has a value of one;
cause a fault, if the check fails; and
update the SSP register with an SSP having a least significant bit replaced with a value of zero, if the check succeeds.
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