US 12,001,842 B2
Hardware apparatuses and methods to switch shadow stack pointers
Vedvyas Shanbhogue, Austin, TX (US); Jason W. Brandt, Austin, TX (US); Ravi L. Sahita, Portland, OR (US); Barry E. Huntley, Hillsboro, OR (US); Baiju V. Patel, Portland, OR (US); and Deepak K. Gupta, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on May 26, 2023, as Appl. No. 18/324,788.
Application 18/324,788 is a continuation of application No. 17/340,632, filed on Jun. 7, 2021, granted, now 11,663,006, issued on May 30, 2023.
Application 17/340,632 is a continuation of application No. 16/534,970, filed on Aug. 7, 2019, granted, now 11,029,952, issued on Jun. 8, 2021.
Application 16/534,970 is a continuation of application No. 14/975,840, filed on Dec. 20, 2015, granted, now 10,394,556, issued on Aug. 27, 2019.
Prior Publication US 2024/0078111 A1, Mar. 7, 2024
Int. Cl. G06F 9/30 (2018.01); G06F 9/46 (2006.01); G06F 21/52 (2013.01)
CPC G06F 9/3004 (2013.01) [G06F 9/30134 (2013.01); G06F 9/461 (2013.01); G06F 21/52 (2013.01)] 33 Claims
OG exemplary drawing
 
1. A processor comprising:
a shadow stack pointer (SSP) register to store a current SSP for a current shadow stack;
a decode unit to decode an instruction to switch from the current shadow stack to a new shadow stack, the instruction having a memory operand to provide a memory address of a token stored on the new shadow stack; and
an execution unit coupled with the decode unit, the execution unit to perform operations corresponding to the instruction, including to:
load the token from the new shadow stack;
check that a portion of the token matches a portion of the memory address and that a least significant bit of the token has a value of one;
cause a fault, if the check fails; and
update the SSP register with an SSP having a least significant bit replaced with a value of zero, if the check succeeds.