US 12,001,810 B2
Signal processing circuit, signal processing device, and signal processing method to suppress power consumption
Tomohiro Matsumoto, Kanagawa (JP); Yusuke Oike, Kanagawa (JP); Akito Sekiya, Kanagawa (JP); Hiroyuki Yamagishi, Kanagawa (JP); and Ryoji Ikegaya, Kanagawa (JP)
Assigned to SONY CORPORATION, Tokyo (JP)
Appl. No. 17/250,314
Filed by SONY CORPORATION, Tokyo (JP)
PCT Filed Jul. 10, 2019, PCT No. PCT/JP2019/027339
§ 371(c)(1), (2) Date Dec. 31, 2020,
PCT Pub. No. WO2020/013226, PCT Pub. Date Jan. 16, 2020.
Claims priority of application No. 2018-131664 (JP), filed on Jul. 11, 2018.
Prior Publication US 2021/0286591 A1, Sep. 16, 2021
Int. Cl. G06F 7/544 (2006.01); G06N 3/063 (2023.01); H02J 7/34 (2006.01); H03K 5/26 (2006.01); H03K 19/21 (2006.01)
CPC G06F 7/5443 (2013.01) [H03K 5/26 (2013.01); G06N 3/063 (2013.01); H02J 7/345 (2013.01); H03K 19/21 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A signal processing circuit, comprising:
a plurality of first circuits each including a first time-length signal output circuit and a second time-length signal output circuit, wherein
the first time-length signal output circuit is configured to output a first time-length signal representing a time length between first timing at which a first input signal changes and second timing at which a second input signal changes, and
the second time-length signal output circuit is configured to output the first time-length signal as a second time-length signal at timing based on a control signal; and
a second circuit configured to output the second time-length signal having the longest time length among a plurality of second time-length signals output respectively from the plurality of first circuits.