US 12,001,768 B1
Enhanced glitch estimation in vectorless power analysis
Qing Su, Sunnyvale, CA (US); Pankaj Singla, Charkhi Dadri (IN); Solaiman Rahim, San Francisco, CA (US); Eduard Petrus Huijbregts, Eindhoven (NL); and Stephan Houben, Heythuysen (NL)
Assigned to SYNOPSYS, INC., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Sunnyvale, CA (US)
Filed on Aug. 25, 2021, as Appl. No. 17/411,578.
Claims priority of provisional application 63/070,044, filed on Aug. 25, 2020.
Int. Cl. G06F 30/3312 (2020.01); G06F 30/3315 (2020.01); G06F 119/12 (2020.01)
CPC G06F 30/3312 (2020.01) [G06F 30/3315 (2020.01); G06F 2119/12 (2020.01)] 18 Claims
OG exemplary drawing
 
1. A method, comprising:
acquiring timing analysis data associated with a cell of a design of an integrated circuit and activity data of one or more inputs of the cell;
determining, by a processor, a glitch toggle rate for an output of the cell based on the activity data of the one or more inputs of the cell and the timing analysis data, wherein the determining the glitch toggle rate comprises:
computing a total toggle rate for the cell using a stochastic simulation, based on static probabilities and toggle rates of the one or more inputs of the cell and based on an inertial delay of the cell;
computing a functional toggle rate based on the one or more inputs of the cell; and
computing the glitch toggle rate based on the total toggle rate and the functional toggle rate;
adjusting the glitch toggle rate based on a correction term for two or more simultaneous toggles on inputs of the cell; and
estimating, by the processor, a glitch power of the design of the integrated circuit based on at least the glitch toggle rate.