US 12,001,727 B2
Techniques for managed NAND translation with embedded memory systems
Wanmo Wong, Menlo Park, CA (US); and Brady L. Keays, Kuna, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 27, 2021, as Appl. No. 17/458,781.
Claims priority of provisional application 63/071,756, filed on Aug. 28, 2020.
Prior Publication US 2022/0066945 A1, Mar. 3, 2022
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0688 (2013.01) [G06F 3/061 (2013.01); G06F 3/0661 (2013.01)] 27 Claims
OG exemplary drawing
 
10. A method performed by a system, comprising:
generating, at a host system, a first command according to a first protocol, the first command to access a logical memory address associated with a memory system;
determining, after generating the first command according to the first protocol, that the memory system uses a second protocol;
identifying, via a first driver at the host system, a physical memory address of the memory system based at least in part on determining that the memory system uses the second protocol;
outputting, via the first driver at the host system, (i) a second command according to the second protocol and (ii) the physical memory address of the memory system based at least in part on generating the first command;
outputting, via a second driver at the host system and based at least in part on the second command, a third command to a third driver;
outputting, via the third driver at the host system to the memory system, a fourth command to the memory system and based at least in part on the third command, the third driver configured to communicate with the memory system according to the second protocol;
receiving, at the memory system, the fourth command and the physical memory address, wherein the physical memory address is communicated according to the second protocol associated with a multi-media controller at the memory system; and
accessing, at the memory system, memory cells in a memory device associated with the physical memory address based at least in part on receiving the fourth command and the physical memory address.