| CPC G06F 3/0659 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0656 (2013.01); G06F 3/0679 (2013.01)] | 25 Claims |
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1. A memory device, comprising:
a memory;
a translation component that is configured to store a mapping of logical addresses to physical addresses associated with the memory, wherein the logical addresses and the physical addresses are associated with a first size associated with a first logical unit, wherein the first logical unit includes a group of second logical units, and wherein the translation component is configured to:
determine, based on the mapping, a physical address associated with a logical address of first data indicated by a write command,
wherein the first data has a size that is less than the first size associated with the first logical unit,
wherein the logical address is associated with a second size that is associated with the second logical units, and
wherein the physical address is associated with the first size; and
determine a set of physical addresses having the second size based on the logical address of the first data;
a read component configured to:
read stored second data, from the memory, corresponding to the set of physical addresses; and
a write command execution component that is configured to operate using the first logical unit, and wherein the write command execution component is configured to:
allocate a set of buffers for the write command,
wherein a quantity of buffers included in the set of buffers is based on a quantity of the second logical units included in the group;
store the first data in at least one buffer from the set of buffers;
merge the second data into the set of buffers; and
cause the first data and the second data stored in the set of buffers to be written to the memory.
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