US 12,001,711 B2
Determine link startup sequence (LSS) type using reference clock frequency and attribute
Rotem Sela, Sunnyvale, CA (US); and Shemmer Choresh, Tel-Aviv (IL)
Assigned to Western Digital Technologies, Inc., San Jose, CA (US)
Filed by Western Digital Technologies, Inc., San Jose, CA (US)
Filed on Jul. 27, 2022, as Appl. No. 17/875,054.
Claims priority of provisional application 63/226,080, filed on Jul. 27, 2021.
Prior Publication US 2023/0035584 A1, Feb. 2, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0655 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A data storage device, comprising:
a memory device; and
a controller coupled to the memory device, the controller configured to:
set first default link attributes to a first frequency at a first power on, wherein the first default link attributes is a pulse width modulation (PWM) link startup sequence (LSS);
receive a host reference clock signal from a host device, wherein the host reference clock signal has a second frequency and second default link attributes different from the first default link attributes, wherein the second default link attributes is a high speed (HS) LSS;
determine that the second frequency is higher than the first frequency;
ignore the first frequency;
operate at the second frequency while maintaining the first default link attributes; and
change from the first default link attributes to the second default link attributes at a second power on.