US 12,001,708 B2
In-memory associative processing for vectors
Sean S. Eilert, Penryn, CA (US); Ameen D. Akel, Rancho Cordova, CA (US); Justin Eno, El Dorado Hills, CA (US); and Brian Hirano, Longmont, CO (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jan. 13, 2022, as Appl. No. 17/647,944.
Claims priority of provisional application 63/239,112, filed on Aug. 31, 2021.
Prior Publication US 2023/0065783 A1, Mar. 2, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0655 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01)] 37 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a memory die comprising a plurality of tiles each comprising a plurality of planes, wherein each plane comprises a respective array of content-addressable memory cells; and
logic coupled with the memory die and configured to:
perform, using associative processing, a computational operation on data representative of a first set of contiguous bits of a vector that is an operand for the computational operation, the data representative of the first set of contiguous bits stored in a first plane of a tile of the plurality of tiles; and
perform, using associative processing, the computational operation on data representative of a second set of contiguous bits of the vector based at least in part on performing the computational operation on the data representative of the first set of contiguous bits, the data representative of the second set of contiguous bits stored in a second plane of the tile of the plurality of tiles.