US 12,001,706 B2
Predictive sanitization of an array of memory with capacitive cells and/or ferroelectric cells
Marco Sforzin, Milan (IT); Angelo Visconti, Appiano Gentile (IT); Giorgio Servalli, Fara Gera d'Adda (IT); Daniele Balluchi, Milan (IT); and Paolo Amato, Treviglio (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 30, 2022, as Appl. No. 17/854,639.
Claims priority of provisional application 63/301,985, filed on Jan. 21, 2022.
Prior Publication US 2023/0236753 A1, Jul. 27, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0652 (2013.01) [G06F 3/0616 (2013.01); G06F 3/0673 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A computing system comprising:
a memory system in communication with a host, and configured to store data therein, the memory system comprising:
a memory including a plurality of memory components coupled to a memory controller via a memory interface; and
the memory controller configured to communicate with the memory to control data transmission and configured to: (i) perform a scrubbing operation of the memory components, and (ii) detect a region of the memory to be sanitized and perform a sanitization operation of the detected region to prevent the occurrence of failure;
wherein the memory controller is further configured to, when detecting the region of the memory to be sanitized:
(a) determine any regions that are about to cross a minimum window limit having a threshold reference, to observe any error for correction and write back data to prevent an accumulation of errors; and
(b) reduce a margin of the minimum window limit and predict whether the detected region will have at least one error in the future.