US 12,001,701 B2
Storage biasing for solid state drive accelerators
Ramanathan Muthiah, Bangalore (IN)
Assigned to Western Digital Technologies, Inc., San Jose, CA (US)
Filed by Western Digital Technologies, Inc., San Jose, CA (US)
Filed on Jan. 26, 2022, as Appl. No. 17/585,410.
Prior Publication US 2023/0236750 A1, Jul. 27, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/064 (2013.01) [G06F 3/0613 (2013.01); G06F 3/0659 (2013.01); G06F 3/0688 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A device, comprising:
a processor;
a memory comprising a plurality of non-volatile NAND flash memory devices configured into a plurality of blocks;
a first accelerator
comprising a throughput and configured to directly access the memory bypassing the processor;
the processor configured to assigns a portion of the memory as a data structure to the first accelerator based on a throughput of the first accelerator;
the first accelerator operating upon data words of a first width in a first mode and operating upon data words of a second width in a second mode;
the second width greater than the first width;
the processor assigning a data structure to the first accelerator in the first mode, wherein:
the data structure is distributed over a first portion of the plurality of non-volatile memory devices;
the processor assigning a data structure to the first accelerator in the second mode, wherein the data structure is distributed over a second portion of the plurality of non-volatile memory devices; and
wherein the second portion is greater than the first portion.