CPC G06F 3/0634 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G11C 7/1069 (2013.01); G11C 7/222 (2013.01); H01L 25/18 (2013.01)] | 20 Claims |
1. An operating method of a memory device including a memory cell array including a first bank region and a second bank region, the operating method comprising:
receiving, at the memory device, a first active command and first address information;
setting, using a mode controller, a mode of the first bank region to an operation mode based on decoding the first active command and the first address information;
enabling, using a first mode signal generator, one or more first processing elements (PEs) corresponding to the first bank region;
disabling, using a second mode signal generator, one or more second PEs corresponding to the second bank region; and
performing an operation for the first bank region by the enabled one or more first PEs,
wherein, while the first bank region is operated in the operation mode, the second bank region is operated in a normal mode.
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