CPC G06F 3/0634 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0611 (2013.01); G06F 3/0625 (2013.01); G06F 3/0638 (2013.01); G06F 3/0673 (2013.01); G06F 3/0683 (2013.01); G06F 12/02 (2013.01); G06F 12/0607 (2013.01); G06F 15/781 (2013.01); G06F 12/0646 (2013.01); G06F 13/4282 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/1028 (2013.01); Y02D 10/00 (2018.01)] | 17 Claims |
1. A system-on-chip comprising:
a first memory port;
a second memory port;
a memory controller configured to access a first memory device through the first memory port or a second memory device through the second memory port;
a processor configured to generate memory addresses for accessing a memory region and configured to generate a control signal for selecting a linear mode and a interleave mode, and, when the memory addresses are greater than a base address, the processor generates the control signal such that the linear mode is selected; and
an address remapping logic configured to, in the linear mode, remap the memory addresses into remapped addresses based on the control signal,
wherein the memory controller is further configured to, in the linear mode, perform a first linear access operation on a first region of the memory region by accessing only the first memory device through the first memory port in response to first remapped addresses of the remapped addresses.
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