US 12,001,697 B2
Multi-modal refresh of dynamic, random-access memory
Thomas Vogelsang, Mountain View, CA (US); Steven C. Woo, Saratoga, CA (US); and Michael Raymond Miller, Raleigh, NC (US)
Assigned to Rambus Inc., San Jose, CA (US)
Filed by Rambus Inc., San Jose, CA (US)
Filed on Oct. 15, 2021, as Appl. No. 17/503,058.
Claims priority of provisional application 63/109,743, filed on Nov. 4, 2020.
Prior Publication US 2022/0137843 A1, May 5, 2022
Int. Cl. G06F 3/00 (2006.01); G06F 3/06 (2006.01)
CPC G06F 3/0634 (2013.01) [G06F 3/061 (2013.01); G06F 3/0673 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) device comprising:
stacked and bonded memory dies, each memory die having:
a first memory-die request interface to a first set of memory banks; and
a second memory-die request interface to a second set of memory banks;
wherein each of the first and second sets of memory banks include volatile memory cells;
a controller die bonded to the memory dies, the controller die including:
a first controller to issue first refresh requests to the first memory-die request interfaces of the bonded memory dies; and
a second controller to issue second refresh requests to the second memory-die request interfaces of the bonded memory dies to issue second refresh requests to the second set of memory banks:
a first refresh-address counter to issue first bank addresses; and
a first bank-address demultiplexer having:
a first demultiplexer input port coupled to the first refresh-address counter to receive the first bank addresses;
a first demultiplexer output port coupled to the first and second memory-die request interfaces of a first of the memory dies; and
a second demultiplexer output port coupled to the first memory-die request interfaces of the first of the memory dies and a second of the memory dies.