US 12,001,696 B2
Channel architecture for memory devices
Reshmi Basu, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jul. 21, 2022, as Appl. No. 17/869,941.
Application 17/869,941 is a continuation of application No. 16/442,902, filed on Jun. 17, 2019, granted, now 11,409,450.
Prior Publication US 2022/0357862 A1, Nov. 10, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 13/40 (2006.01); G06F 3/06 (2006.01); G06F 13/36 (2006.01); G06N 20/00 (2019.01)
CPC G06F 3/0632 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G06N 20/00 (2019.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
an interface coupled to a plurality of channels; and
a controller coupled to the interface, wherein the controller is configured to:
determine an aggregate amount of front end bandwidth used by a plurality of applications accessing data from a memory device coupled to the controller via the plurality of channels;
determine, based on the aggregate amount of front end bandwidth used by the plurality of applications, a front end bandwidth demand for the plurality of applications;
disable one or more channels of the plurality of channels based, at least in part, on the aggregate amount of front end bandwidth used by the plurality of applications in accessing the data from the memory device; and
re-enable a sub-set of channels among the one or more disabled channels to fulfil the front end bandwidth demand.