US 12,001,693 B2
Data storage device with noise injection
Daniel Joseph Linnen, Naperville, IL (US); Kirubakaran Periyannan, Saratoga, CA (US); and Ramanathan Muthiah, Bangalore (IN)
Assigned to Western Digital Technologies, Inc., San Jose, CA (US)
Filed by Western Digital Technologies, Inc., San Jose, CA (US)
Filed on Jun. 22, 2022, as Appl. No. 17/847,068.
Prior Publication US 2023/0418481 A1, Dec. 28, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0628 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0619 (2013.01); G06F 3/0679 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A device formed on a die, comprising:
a non-volatile memory (NVM) array formed on the die; and
processing circuitry formed on the die and configured to:
determine a noise-reducing read voltage level that reduces an amount of noise occurring within data read from the NVM array;
set a first read voltage level to a level different from the noise-reducing read voltage level to add noise into data to be read from the NVM array, wherein the added noise is greater than an amount of noise occurring using the noise-reducing read voltage level;
read data from the NVM array using the first read voltage level set to add noise into the data to obtain a noisy version of the data;
obtain corresponding data without added noise;
compare the corresponding data with the noisy version of the data to determine an amount of noise added to the data by using the first read voltage level;
receive a value specifying an amount of noise to be added into additional data read from the NVM array;
adjust the first read voltage level to a second read voltage level based on the received value; and
read the additional data from the NVM array using the second re ad voltage level to add the specified amount of noise into the additional data read from the NVM array.