US 12,001,678 B2
Address translation metadata compression in memory devices
Brian Toronyi, Boulder, CO (US); and Scheheresade Virani, Frisco, TX (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 25, 2022, as Appl. No. 17/895,696.
Prior Publication US 2024/0069728 A1, Feb. 29, 2024
Int. Cl. G06F 3/06 (2006.01); G06F 12/02 (2006.01); G06F 12/1009 (2016.01)
CPC G06F 3/0608 (2013.01) [G06F 3/0629 (2013.01); G06F 3/0679 (2013.01); G06F 12/0246 (2013.01); G06F 12/1009 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
receiving, by a controller managing a memory device, a memory access request specifying a logical address of a data item and a memory access operation to be performed with respect to the data item;
identifying, in an address translation table, an address translation table entry referenced by the logical address;
determining a truncated physical address specified by the address translation table entry;
restoring an original physical address from the truncated physical address, wherein the original physical address specifies a location of the data item on the memory device; and
performing the memory access operation using the original physical address.