US 12,001,375 B2
Interconnect system
Weilin Wang, Beijing (CN); Xiaoliang Kang, Shaanxi Province (CN); Xuemin Zhang, Shanghai (CN); Chen Chen, Beijing (CN); and Yang Shi, Beijing (CN)
Assigned to SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD., Shanghai (CN)
Filed by Shanghai Zhaoxin Semiconductor Co., Ltd., Shanghai (CN)
Filed on Nov. 10, 2021, as Appl. No. 17/523,049.
Claims priority of application No. 202111141627.5 (CN), filed on Sep. 28, 2021; application No. 202111142578.7 (CN), filed on Sep. 28, 2021; application No. 202111142579.1 (CN), filed on Sep. 28, 2021; and application No. 202111142604.6 (CN), filed on Sep. 28, 2021.
Prior Publication US 2023/0101918 A1, Mar. 30, 2023
Int. Cl. G06F 13/42 (2006.01); G06F 1/3234 (2019.01); G06F 9/4401 (2018.01); G06F 9/48 (2006.01); G06F 13/16 (2006.01); G06F 13/40 (2006.01); G06F 15/78 (2006.01); H04L 1/00 (2006.01); H04L 45/00 (2022.01); H04L 45/02 (2022.01); H04L 45/42 (2022.01); H04L 45/745 (2022.01); H04L 69/324 (2022.01)
CPC G06F 13/4265 (2013.01) [G06F 1/3234 (2013.01); G06F 9/4418 (2013.01); G06F 9/4812 (2013.01); G06F 13/1668 (2013.01); G06F 13/4027 (2013.01); G06F 13/4068 (2013.01); G06F 15/7807 (2013.01); G06F 15/7825 (2013.01); H04L 1/004 (2013.01); H04L 45/02 (2013.01); H04L 45/22 (2013.01); H04L 45/42 (2013.01); H04L 45/745 (2013.01); H04L 69/324 (2013.01); G06F 13/4208 (2013.01); G06F 13/4282 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A interconnect system, comprising a plurality of sockets and a first interconnect interface, wherein any two of the sockets are accessible to each other's hardware resources by transmitting a first packet and a second packet through the first interconnect interface;
wherein the first packet comprises first interconnect information, configured for establishing communication that conforms with a communication protocol of the first interconnect interface between any two of the sockets;
wherein the second packet comprises a first data payload, the first data payload is data loaded from one of the sockets and transmitted to another one;
wherein the sockets comprise a first socket and a second socket, configured to be interconnected with each other through the first interconnect interface; and
wherein the number of bits of the first data payload when the first interconnect interface is congested is bigger than the number of bits of the first data payload when the first interconnect interface is not congested.