US 12,001,374 B2
System and method for providing in-storage acceleration (ISA) in data storage devices
Ramdas Kachare, San Jose, CA (US); Fred Worley, San Jose, CA (US); and Xuebin Yao, San Jose, CA (US)
Assigned to Samsung Electronics Co., Ltd., Yongin-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Sep. 26, 2022, as Appl. No. 17/953,011.
Application 17/953,011 is a continuation of application No. 16/928,711, filed on Jul. 14, 2020, granted, now 11,487,696.
Application 16/928,711 is a continuation of application No. 15/921,400, filed on Mar. 14, 2018, granted, now 10,719,474, issued on Jul. 21, 2020.
Claims priority of provisional application 62/571,061, filed on Oct. 11, 2017.
Claims priority of provisional application 62/571,064, filed on Oct. 11, 2017.
Prior Publication US 2023/0016328 A1, Jan. 19, 2023
Int. Cl. G06F 3/06 (2006.01); G06F 9/4401 (2018.01); G06F 13/16 (2006.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01); H04L 49/356 (2022.01); G06N 20/00 (2019.01)
CPC G06F 13/4234 (2013.01) [G06F 3/0611 (2013.01); G06F 3/0632 (2013.01); G06F 3/0659 (2013.01); G06F 3/067 (2013.01); G06F 9/4411 (2013.01); G06F 13/1668 (2013.01); G06F 13/4027 (2013.01); G06F 13/4221 (2013.01); G06F 13/4295 (2013.01); H04L 49/356 (2013.01); G06F 2213/0008 (2013.01); G06F 2213/0026 (2013.01); G06N 20/00 (2019.01)] 20 Claims
OG exemplary drawing
 
1. A bridge device comprising:
a first interface for accessing data stored in a non-transitory data storage medium of a data storage device;
a processor;
a processing circuit;
an interconnect;
a second interface for receiving a command from a computing device for configuring the data storage device to run a first process in the bridge device, wherein the command includes first configuration data, first instructions and a first identifier; and
a controller for reconfiguring at least one of a first portion of the processing circuit associated with the first identifier or the interconnect by loading first configuration data into the processing circuit and interconnecting the processing circuit via the interconnect,
wherein the controller is configured to receive the command via the second interface and load the processor with the first instructions,
wherein the processor is configured to run the first process by accessing the data stored in the non-transitory data storage medium of the data storage device via the first interface and process the data using the first portion of the processing circuit and the interconnect that are reconfigured by the controller according to the command,
wherein the controller is configured to receive second configuration data, second instructions, and a second identifier, and configure a second portion of the processing circuit associated with the second identifier based on the second configuration data, and load the second instructions to the processor for running a second process based on the second configuration data and the second instructions.