US 12,001,373 B2
Dynamic allocation of peripheral component interconnect express bus numbers
Wei G. Liu, Austin, TX (US); Alberto D. Perez Guevara, Pflugerville, TX (US); and Sanjeev Singh, Cedar Park, TX (US)
Assigned to Dell Products L.P., Round Rock, TX (US)
Filed by Dell Products L.P., Round Rock, TX (US)
Filed on Jun. 16, 2022, as Appl. No. 17/842,384.
Prior Publication US 2023/0409505 A1, Dec. 21, 2023
Int. Cl. G06F 13/42 (2006.01); G06F 9/50 (2006.01)
CPC G06F 13/4221 (2013.01) [G06F 9/5044 (2013.01); G06F 2213/0026 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method performed at power-on self-test, the method comprising:
detecting, by a processor, whether each one of a plurality of peripheral component interconnect express (PCIe) slots is populated or unpopulated;
updating a PCIe bus configuration map to indicate whether each one of the PCIe slots is populated or unpopulated;
allocating PCIe bus resources to each one of the PCIe slots based on the PCIe bus configuration map, wherein the allocating of the PCIe bus resources includes prioritizing populated PCIe slots over unpopulated PCIe slots; and
disabling a root port associated with an unpopulated PCIe slot.