US 12,001,367 B2
Multi-die integrated circuit with data processing engine array
Juan J. Noguera Serra, San Jose, CA (US); Tim Tuan, San Jose, CA (US); and Sridhar Subramanian, San Jose, CA (US)
Assigned to Xilinx, Inc., San Jose, CA (US)
Filed by Xilinx, Inc., San Jose, CA (US)
Filed on May 18, 2023, as Appl. No. 18/320,147.
Application 18/320,147 is a continuation of application No. 17/654,543, filed on Mar. 11, 2022, granted, now 11,693,808.
Application 17/654,543 is a continuation of application No. 17/035,368, filed on Sep. 28, 2020, granted, now 11,288,222, issued on Mar. 29, 2022.
Prior Publication US 2023/0289311 A1, Sep. 14, 2023
Int. Cl. G06F 13/40 (2006.01); G06F 13/16 (2006.01)
CPC G06F 13/4027 (2013.01) [G06F 13/1668 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A multi-die integrated circuit, comprising:
an interposer;
a die coupled to the interposer, wherein the die includes a first data processing engine (DPE) array and a second DPE array;
wherein the first DPE array includes a first plurality of DPEs and a first DPE interface coupled to the first plurality of DPEs;
wherein the second DPE array includes a second plurality of DPEs and a second DPE interface coupled to the second plurality of DPEs; and
one or more other dies having a first die interface coupled to, and configured to communicate with, the first DPE interface via the interposer and a second die interface coupled to, and configured to communicate with, the second DPE interface via the interposer.