US 12,001,364 B2
System for link management between multiple communication chips
Helena Deirdre O'Shea, San Jose, CA (US); Camille Chen, Cupertino, CA (US); Vijay Kumar Ramamurthi, Milpitas, CA (US); Alon Paycher, Beit Hanania (IL); Matthias Sauer, San Jose, CA (US); and Bernd W. Adler, San Jose, CA (US)
Assigned to APPLE INC., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Mar. 21, 2023, as Appl. No. 18/124,332.
Application 18/124,332 is a continuation of application No. 17/500,325, filed on Oct. 13, 2021, granted, now 11,640,365.
Application 17/500,325 is a continuation of application No. 16/885,889, filed on May 28, 2020, granted, now 11,176,069, issued on Nov. 16, 2021.
Claims priority of provisional application 62/957,048, filed on Jan. 3, 2020.
Prior Publication US 2023/0222076 A1, Jul. 13, 2023
Int. Cl. G06F 13/362 (2006.01); G06F 11/30 (2006.01); G06F 11/34 (2006.01); G06F 13/24 (2006.01); G06F 13/28 (2006.01); G06F 13/40 (2006.01)
CPC G06F 13/3625 (2013.01) [G06F 11/3051 (2013.01); G06F 11/3409 (2013.01); G06F 13/24 (2013.01); G06F 13/28 (2013.01); G06F 13/4068 (2013.01); G06F 2213/0038 (2013.01); G06F 2213/40 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A first integrated circuit, comprising:
an interface circuit configured to communicate with a second integrated circuit over a multi-drop bus in an electronic device; and
a processor circuit configured to:
send a notify signal to a third integrated circuit over a first configurable direct connection separate from the multi-drop bus, the notify signal indicating assumed authorization for executing an activity at the first integrated circuit,
receive a request from the second integrated circuit over a second configurable direct connection separate from the multi-drop bus, the request associated with timing information indicating a time when one or more resources become available for release by the first integrated circuit, and
responsive to the received request, send a response to the second integrated circuit over the second configurable direct connection informing the second integrated circuit about the time when the one or more resources become available for release.