CPC G06F 13/3625 (2013.01) [G06F 11/3051 (2013.01); G06F 11/3409 (2013.01); G06F 13/24 (2013.01); G06F 13/28 (2013.01); G06F 13/4068 (2013.01); G06F 2213/0038 (2013.01); G06F 2213/40 (2013.01)] | 20 Claims |
1. A first integrated circuit, comprising:
an interface circuit configured to communicate with a second integrated circuit over a multi-drop bus in an electronic device; and
a processor circuit configured to:
send a notify signal to a third integrated circuit over a first configurable direct connection separate from the multi-drop bus, the notify signal indicating assumed authorization for executing an activity at the first integrated circuit,
receive a request from the second integrated circuit over a second configurable direct connection separate from the multi-drop bus, the request associated with timing information indicating a time when one or more resources become available for release by the first integrated circuit, and
responsive to the received request, send a response to the second integrated circuit over the second configurable direct connection informing the second integrated circuit about the time when the one or more resources become available for release.
|