CPC G06F 13/36 (2013.01) [G06F 1/10 (2013.01)] | 20 Claims |
1. An integrated circuit arranged among a plurality of integrated circuits, the integrated circuit comprising:
an identification circuit configured to derive a topologically unique identifier by performing an input measurement of a stimulus provided by a host circuit, wherein the topologically unique identifier is set using a plurality of pull values that are arranged such that no repeated sequence of pull values exists in a detectable chain of pull values associated with other integrated circuits within the plurality of integrated circuits, wherein the integrated circuit is topologically indistinguishable from at least one other integrated circuit of the plurality of integrated circuits from a perspective of the host circuit, wherein the integrated circuit and the other integrated circuits within the plurality of integrated circuits are communicably coupled with the host circuit via a shared communication bus, wherein the input measurement comprises a binary input measurement or a non-binary input measurement based on one or more values comprising one or more of a pin voltage, a supply voltage, or a pin logic level of the integrated circuit, and wherein, responsive to resetting or powering on the integrated circuit, the identification circuit is further configured to receive topologically unique data from the host circuit.
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