	US 12,001,346 B2
	Device, method and system to supplement a skewed cache with a victim cache
Thomas Unterluggauer, Hillsboro, OR (US); Alaa Alameldeen, Hillsboro, OR (US); Scott Constable, Portland, OR (US); Fangfei Liu, Hillsboro, OR (US); Francis McKeen, Portland, OR (US); Carlos Rozas, Portland, OR (US); and Anna Trikalinou, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 18, 2020, as Appl. No. 17/127,786.
Prior Publication US 2022/0200783 A1, Jun. 23, 2022
Int. Cl. G06F 12/10 (2016.01); G06F 12/121 (2016.01); G06F 12/14 (2006.01)

CPC G06F 12/14 (2013.01) [G06F 12/121 (2013.01); G06F 2212/1052 (2013.01)]

20 Claims

1. An integrated circuit comprising:

first circuitry to:

receive a first message which indicates a first address which corresponds to a first line of data; and

identify a first location of a skewed cache based on the message;

second circuitry coupled to the first circuitry, wherein, based on the first message, the second circuitry is to:

move a second line from the first location to a second location of a second cache; and

store the first line to the first location;

wherein the first circuitry is further to receive a second message which indicates a second address which corresponds to the second line; and

wherein the second circuitry is further to move the second line from the second location to the skewed cache based on the second message.