US 12,001,342 B2
Isolated performance domains in a memory system
Anirban Ray, Santa Clara, CA (US); and Parag R. Maharana, Dublin, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 11, 2022, as Appl. No. 17/693,130.
Application 17/693,130 is a continuation of application No. 16/893,757, filed on Jun. 5, 2020, granted, now 11,275,696.
Application 16/893,757 is a continuation of application No. 16/035,469, filed on Jul. 13, 2018, granted, now 10,691,611, issued on Jun. 23, 2020.
Prior Publication US 2022/0197820 A1, Jun. 23, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/1009 (2016.01); G06F 9/30 (2018.01); G06F 9/455 (2018.01); G06F 9/50 (2006.01); G06F 12/02 (2006.01)
CPC G06F 12/1009 (2013.01) [G06F 9/30003 (2013.01); G06F 9/45558 (2013.01); G06F 9/5016 (2013.01); G06F 12/0246 (2013.01); G06F 2009/45583 (2013.01); G06F 2212/657 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A computing system, comprising:
a plurality of memory components including a first memory and a second memory; and
a processing device, operatively coupled with the plurality of memory components, to:
store a memory allocation value;
provision an amount of the second memory;
limit an amount of first memory via the allocation value;
access the amount of the second memory via the amount of the first memory;
wherein the amount of the second memory is provisioned for executing a set of instructions, and the amount of the second memory is accessed, during the execution of the set of instructions, via the amount of the first memory.