US 12,001,340 B2
Full multi-plane operation enablement
Jiangang Wu, Milpitas, CA (US); Qisong Lin, El Dorado Hills, CA (US); Jung Sheng Hoei, Newark, CA (US); Yunqiu Wan, Palo Alto, CA (US); Ashutosh Malshe, Fremont, CA (US); and Peng-Cheng Chen, Lost Gatos, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 21, 2023, as Appl. No. 18/124,447.
Application 18/124,447 is a continuation of application No. 16/730,881, filed on Dec. 30, 2019, granted, now 11,615,029.
Prior Publication US 2023/0297511 A1, Sep. 21, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/00 (2006.01); G06F 11/14 (2006.01); G06F 12/02 (2006.01); G06F 12/0811 (2016.01); G06F 12/0882 (2016.01); G06F 12/0891 (2016.01); G06F 13/16 (2006.01); G11C 16/06 (2006.01)
CPC G06F 12/0891 (2013.01) [G06F 11/14 (2013.01); G06F 12/0246 (2013.01); G06F 12/0811 (2013.01); G06F 12/0882 (2013.01); G06F 13/1668 (2013.01); G11C 16/06 (2013.01)] 20 Claims
OG exemplary drawing
 
9. A memory system, comprising:
processing circuitry associated with one or more memory devices, wherein the processing circuitry is configured to cause the memory system to:
determine that a quantity of planes of a set of planes of a memory die are invalid planes;
duplicate, based on determining the quantity of the invalid planes, commands of one or more valid planes of the set of planes; and
issue, based on duplicating the commands of the one or more valid planes, a single descriptor associated with a multi-plane operation for the set of planes of the memory die, wherein the single descriptor comprises a command sequence for the multi-plane operation.