US 12,001,337 B2
Using physical address proxies to accomplish penalty-less processing of load/store instructions whose data straddles cache line address boundaries
John G. Favor, San Francisco, CA (US); and Srivatsan Srinivasan, Cedar Park, TX (US)
Assigned to Ventana Micro Systems Inc., Cupertino, CA (US)
Filed by Ventana Micro Systems Inc., Cupertino, CA (US)
Filed on May 18, 2022, as Appl. No. 17/747,749.
Application 17/747,749 is a continuation in part of application No. 17/370,009, filed on Jul. 8, 2021, granted, now 11,481,332.
Application 17/370,009 is a continuation in part of application No. 17/351,927, filed on Jun. 18, 2021, granted, now 11,416,406.
Application 17/351,927 is a continuation in part of application No. 17/351,946, filed on Jun. 18, 2021, granted, now 11,397,686.
Application 17/351,946 is a continuation in part of application No. 17/315,262, filed on May 7, 2021, granted, now 11,416,400.
Application 17/370,009 is a continuation in part of application No. 17/351,927, filed on Jun. 18, 2021, granted, now 11,416,406.
Application 17/351,927 is a continuation in part of application No. 17/351,946, filed on Jun. 18, 2021, granted, now 11,397,686.
Application 17/351,946 is a continuation in part of application No. 17/315,262, filed on May 7, 2021, granted, now 11,416,400.
Application 17/351,927 is a continuation in part of application No. 17/315,262, filed on May 7, 2021, granted, now 11,416,400.
Application 17/351,946 is a continuation in part of application No. 17/315,262, filed on May 7, 2021, granted, now 11,416,400.
Claims priority of provisional application 63/331,487, filed on Apr. 15, 2022.
Claims priority of provisional application 63/285,372, filed on Dec. 2, 2021.
Claims priority of provisional application 63/271,934, filed on Oct. 26, 2021.
Prior Publication US 2022/0358045 A1, Nov. 10, 2022
Int. Cl. G06F 12/08 (2016.01); G06F 12/0811 (2016.01); G06F 12/0864 (2016.01)
CPC G06F 12/0864 (2013.01) [G06F 12/0811 (2013.01)] 40 Claims
OG exemplary drawing
 
1. A microprocessor, comprising:
a physically-indexed physically-tagged second-level set-associative cache, wherein each entry of the second-level cache is configured to hold a copy of a line of memory and is uniquely identified by a set index and a way;
a store queue; and
a load/store unit configured to, during execution of a store instruction having store data:
detect that, based on a store virtual address and a data size specified by the store instruction, a first portion of the store data is to be written to a first line of memory specified by a first store physical memory line address and that a second portion of the store data is to be written to a second line of memory different from the first line of memory and specified by a second store physical memory line address;
write all the store data to an entry of the store queue allocated to the store instruction; and
write to the allocated store queue entry first and second store physical address proxies (PAPs) for the first and second store physical memory line addresses, respectively, wherein the first store PAP comprises the set index and way that uniquely identifies an entry of the second-level cache that holds a copy of the first line of memory specified by the first store physical memory line address, wherein the second store PAP comprises the set index and way that uniquely identifies an entry of the second-level cache that holds a copy of the second line of memory specified by the second store physical memory line address;
wherein the entries of the store queue are absent storage for holding the first and second store physical memory line addresses.