US 12,001,317 B2
Waveform based reconstruction for emulation
Gagan Vishal Jain, Milpitas, CA (US); Johnson Adaikalasamy, Sunnyvale, CA (US); Alexander John Wakefield, Fort Lauderdale, FL (US); Ritesh Mittal, Sunnyvale, CA (US); Solaiman Rahim, San Francisco, CA (US); and Olivier Coudert, San Francisco, CA (US)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Sunnyvale, CA (US)
Filed on Jun. 27, 2023, as Appl. No. 18/342,361.
Application 17/454,589 is a division of application No. 15/811,010, filed on Nov. 13, 2017, granted, now 11,200,149, issued on Dec. 14, 2021.
Application 18/342,361 is a continuation of application No. 17/454,589, filed on Nov. 11, 2021, granted, now 11,726,899.
Claims priority of provisional application 62/421,167, filed on Nov. 11, 2016.
Prior Publication US 2023/0342283 A1, Oct. 26, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/36 (2006.01); G06F 30/331 (2020.01)
CPC G06F 11/3652 (2013.01) [G06F 11/3636 (2013.01); G06F 11/3656 (2013.01); G06F 30/331 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A non-transitory computer readable medium comprising stored instructions, the instructions that when executed by a processor cause the processor to:
determine a first portion of a first waveform from waveforms of signals of a plurality of logic circuits, the first waveform associated with a first signal of the signals, the first portion of the first waveform having at least a predetermined number of toggles during predetermined clock cycles of a plurality of clock cycles during emulation of the plurality of logic circuits;
convert the first portion of the first waveform into a plurality of bits, each bit of the plurality of bits representing a state of the first signal during a corresponding clock cycle;
simulate electronically one or more logic circuits of the plurality of logic circuits for first clock cycles of the plurality of clock cycles, the first clock cycles of the plurality of clock cycles corresponding to a second portion of the first waveform;
omit simulation of the one or more logic circuits for second clock cycles of the plurality of clock cycles corresponding to a third portion of the first waveform;
simulate electronically the one or more logic circuits based on the plurality of bits for third clock cycles of the plurality of clock cycles, the third clock cycles of the plurality of clock cycles corresponding to the first portion of the first waveform; and
generate an output waveform of an output signal of a logic circuit from the one or more logic circuits for the plurality of clock cycles based on the simulation of the one or more logic circuits for the first clock cycles and the third clock cycles.