US 12,001,305 B2
Resource allocation for a memory built-in self-test
Scott E. Schaefer, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 16, 2022, as Appl. No. 17/820,128.
Prior Publication US 2024/0061758 A1, Feb. 22, 2024
Int. Cl. G06F 11/27 (2006.01); G06F 9/50 (2006.01)
CPC G06F 11/27 (2013.01) [G06F 9/5044 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A memory device, comprising:
one or more components configured to:
read one or more bits, before performing a memory built-in self-test, that are stored in a mode register of the memory device,
wherein the one or more bits indicate one or more memory resources of the memory device that are to be used for performing the memory built-in self-test;
identify the one or more memory resources of the memory device based on reading the one or more bits,
wherein the one or more memory resources of the memory device are addressable memory resources configured for performing standard memory operations of the memory device; and
perform the memory built-in self-test for the memory device using the one or more memory resources of the memory device,
wherein the one or more memory resources of the memory device are not used for performing the standard memory operations of the memory device based on the one or more bits indicating that the one or more memory resources of the memory device are to be used for performing the memory built-in self-test.