US 12,001,286 B2
Memory device with dynamic processing level calibration
Larry J. Koudele, Erie, CO (US); and Bruce A. Liikanen, Berthoud, CO (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 19, 2022, as Appl. No. 17/748,366.
Application 17/748,366 is a continuation of application No. 16/566,692, filed on Sep. 10, 2019, granted, now 11,354,193.
Application 16/566,692 is a continuation of application No. 15/605,858, filed on May 25, 2017, granted, now 10,452,480, issued on Oct. 22, 2019.
Prior Publication US 2022/0276930 A1, Sep. 1, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/00 (2006.01); G06F 11/07 (2006.01); G06F 11/14 (2006.01); G11C 11/56 (2006.01); G11C 16/26 (2006.01); G11C 29/02 (2006.01); G11C 29/52 (2006.01); G11C 29/44 (2006.01)
CPC G06F 11/142 (2013.01) [G06F 11/073 (2013.01); G11C 11/5642 (2013.01); G11C 16/26 (2013.01); G11C 29/021 (2013.01); G11C 29/028 (2013.01); G11C 29/52 (2013.01); G06F 2201/805 (2013.01); G11C 2029/4402 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system, comprising:
a memory array; and
a processing device coupled to the memory array, the processing device configured to iteratively adjust an active processing level used to process data stored in the memory array, wherein, for each iteration, the controller is configured to:
determine a first set of read results based on the active processing level,
determine a second set of read results based on using an offset processing level different than the active processing level, and
incrementally adjust the active processing level based on a comparison of the first and the second sets of read results.