US 12,001,283 B2
Energy efficient storage of error-correction-detection information
Michael Raymond Miller, Raleigh, NC (US); Stephen Magee, Apex, NC (US); and John Eric Linstadt, Palo Alto, CA (US)
Assigned to Rambus Inc., San Jose, CA (US)
Filed by Rambus Inc., San Jose, CA (US)
Filed on Apr. 4, 2023, as Appl. No. 18/130,810.
Application 18/130,810 is a continuation of application No. 17/734,464, filed on May 2, 2022, granted, now 11,645,152.
Application 17/734,464 is a continuation of application No. 16/881,859, filed on May 22, 2020, granted, now 11,347,587, issued on May 31, 2022.
Application 16/881,859 is a continuation of application No. 15/990,078, filed on May 25, 2018, granted, now 10,705,912, issued on Jul. 7, 2020.
Claims priority of provisional application 62/516,240, filed on Jun. 7, 2017.
Prior Publication US 2023/0297474 A1, Sep. 21, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/10 (2006.01); G06F 3/06 (2006.01)
CPC G06F 11/1076 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0625 (2013.01); G06F 3/0644 (2013.01); G06F 3/0673 (2013.01); G06F 11/1048 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A controller, comprising:
at least three of memory channel interfaces that are to operate independently of accesses that occur via the other of the memory channel interfaces;
the memory channel interfaces including an error detection and correction data channel interface, the controller to open a row of a memory device on the error detection and correction data channel interface that is storing a first group of check bits that are associated with a first data word group and a second group of check bits that are associated with a second data word group;
the memory channel interfaces including a first data channel interface and a second data channel interface, the first data channel interface to access the first data word group that is stored contiguously in a first row of a first memory component that is addressed by a first row address and to access a second data word group that is stored in a second row of a second memory component that is accessed via the second data channel interface; and
the controller to receive, from the row of the memory device that is open, the first group of check bits and the second group of check bits.